1. Field of Invention
The present invention relates to a method for accessing a memory system. More particularly, the present invention relates to an access method used to enhance the throughput by interleaving a multi-rank memory system.
2. Description of Related Art
Generally, data access systems nowadays include a memory unit, and some of the memory units are designed as multi-rank for expanding the memory space in the future. These memory ranks share the same single system bus.
A memory page is a basic unit of a memory access. A memory page should be activated before reading operation, and then a reading command is asserted to the memory after passing some clock cycles. After the memory received the command, the memory waits for a span of time then the desired data can be accessed, where the span of time is so-called latency. It spends many clock cycles between activating a memory page and accessing the data. If the next desired data is in the same memory page with the present accessed data, time of activating memory page can be saved; furthermore, the pipeline schedule can be fully utilized for enhancing the efficiency of the system bus. In contrast, if the next desired data is not in the same memory page with the present accessed data, the activated memory page should be firstly pre-charged and then the another memory page allocating to the next desired data is activated. After spending lots of clock cycles for asserting the accessing command and after waiting for the latency, then the data is ready to be accessed. However, the data bus is idle during those clock cycles and latency, as a result, the data access system is inefficient.
FIG. 1 shows the condition described above. The access cycle 102 is total clock duration for accessing the first data. As shown in FIG. 1, when accessing a first data, the system spends two clock cycles for activating a page, and spends three clock cycles and two clock cycles respectively for waiting latency and accessing the data after asserting a data accessing command. Assuming the following second data which needs to be accessed after the first data is in the different memory page with the first data, the memory page allocating to the first data is pre-charged and the another memory page allocating to the second data is activated. Similarly, an access cycle 104 identical with the access cycle 102 is spent for accessing the second data. In this example, the system spends total nine clock cycles for accessing the second data, and most of the time is spent on the activating and pre-charging.